System and method of analyzing integrated circuit in consideration of a process variation

A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit comprises at least one conducting segment corresponding to one wiring layer or one via,

• the method comprising:
• receiving a technology file and design data of the integrated circuit;
• extracting a plurality of resistances and a plurality of capacitances which correspond to a process variation of the first net;
• counting a number of conducting segments corresponding to the first net from the design data;
• calculating a corner resistance and a corner capacitance of the first net based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances;
• and
• calculating a delay time of the first net based on the corner resistance and the corner capacitance.

A computer implemented method for analyzing a timing of an integrated circuit,

• the method comprising:
• providing a parasitics description file or design data corresponding to a first net of the integrated circuit;
• providing a technology file;
• providing a corner coefficient, wherein the corner coefficient indicates a multiple of a standard deviation according to a process variation;
• counting a number of vias of the first net from the parasitics description file or from the first net;
• and
• calculating a corner resistance of vias in the first net using the counted number of vias, the technology file, and the corner coefficient, wherein the corner resistance indicates a resistance of the vias in the first net that accounts for the process variation.