Error resilient digital signal processing device

A signal processing device comprising:

• a computation circuit configured to use clocked input data to generate first data corresponding to a first clock cycle;
• a logic circuit configured to generate a control signal indicating whether the signal processing device exhibited a timing error during the first clock cycle;
• a selection circuit configured to receive the control signal and, based on whether the control signal indicates that the signal processing device exhibited the timing error during the first clock cycle, provide as output, during a transition from the first clock cycle to a second clock cycle, either the first data or second data that is generated by the computation circuit and corresponds to the second clock cycle;
• a counter configured to count a number of performed computations by the signal processing device according to the control signal and to provide a signal representative of the counted computations;
• and
• a circuit configured to clock the input data and provide the clocked input data,
• wherein the circuit comprises a plurality of timing error detection circuits, wherein each timing error detection circuit is configured to receive one bit of the input data and to provide a local set-up timing error signal if a difference between the one bit of the input data and a clock signal is detected.