In-design real-time electrical impact verification flow

A computer-implemented method of generating a layout of an integrated circuit design, the method comprising:

• performing, using a processor, a pre-layout simulation of the integrated circuit design to generate simulation data;
• extracting, using the processor, characteristics of a plurality of routed interconnections based on layout data of the circuit, wherein the layout data comprises extracted spacing and density information of those regions of the circuit for which layout has been finished and estimated spacing and density information of those regions of the circuit for which layout has not yet been finished;
• using the simulation data and the extracted characteristics of routed interconnections, calculating, using the processor, an electro-migration (EM) and IR drop for each routed interconnection of the plurality of interconnections;
• and
• creating, using the processor, a modified layout of the integrated circuit by changing, using the processor, the layout of the integrated circuit in accordance with electro-migration (EM) and IR drop limits.