Data processing system to implement wiring/silicon blockages via parameterized cells

A method of implementing wiring/silicon blockages via parameterized cells (pCells), the method comprising:

• generating, via a front end-of-line placement/blockage (FEOL P/B) controller, at least one placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC);
• outputting a placement blockage parameter indicating the at least one placement blockage and storing the at least one placement blockage in a wire track allocation database;
• generating, via a back end-of-line wiring track (BEOL WT) controller, a wire track blockage of the IC;
• generating, via a BEOL power track (BEOL PT) controller, a metal blockage within the wire track blockage;
• and
• defining a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC based on a combination of the metal blockage and wire track blockage,
• wherein the concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC is provided for manufacturing the IC, and
• wherein the parent-child contract indicates placement of the child block with respect to a larger parent block, the child block including at least one circuit that is physically contained within bounds of the parent block.

A computer program product configured to implement wiring/silicon blockages via parameterized cells (pCells), the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic pCell processor to cause the pCell processor to:

• generate, via a front end-of-line placement/blockage (FEOL P/B) controller, at least one placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC);
• output a placement blockage parameter indicating the at least one placement blockage and store the at least one placement blockage in a wire track allocation database;
• generate, via a back end-of-line wiring track (BEOL WT) controller, a wire track blockage of the IC;
• generate, via a BEOL power track (BEOL PT) controller, a power pin within the wire track blockage;
• and
• define a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC based on a combination of the metal blockage and wire track blockage,
• wherein the concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC is provided for manufacturing the IC, and
• wherein the parent-child contract indicates placement of the child block with respect to a larger parent block, the child block including at least one circuit that is physically contained within bounds of the parent block.