System design based on unified chip specification

A device comprising:

• a processing unit;
• a memory coupled to the processing unit and storing instructions thereon, the instructions, when executed by the processing unit, performing operations including:
• determining, based on a system design for a system, that a first interface of a first chip is to be connected to a second interface of a second chip;
• determining a first configuration of the first interface based on a unified specification, the unified specification at least specifying configurations of a plurality of chip interfaces for respective usages;
• determining a second configuration of the second interface based on the unified specification;
• determining a first plurality of registers of the first interface and a second plurality of registers of the second interface involved in a hardware-level connection based on the unified specification;
• configuring the first plurality of registers and the second plurality of registers based on the unified specification;
• automatically generating a hardware design for the system based on the first and second configurations, the hardware design including the hardware-level connection between the first and second interfaces;
• and
• automatically generating a schematic for the system based on the first and second configurations, the schematic including connections between a first plurality of pins of the first interface and a second plurality of pins of the second interface.

A computer program product being tangibly stored on a non-transient machine-readable medium and comprising machine-executable instructions, the instructions, when executed on a device, causing the device to:

• determine, based on a system design for a system, that a first interface of a first chip is to be connected to a second interface of a second chip;
• determine a first configuration of the first interface based on a unified specification, the unified specification at least specifying configurations of a plurality of chip interfaces for respective usages;
• determine a second configuration of the second interface based on the unified specification;
• determining a first plurality of registers of the first interface and a second plurality of registers of the second interface involved in a hardware-level connection based on the unified specification;
• configuring the first plurality of registers and the second plurality of registers based on the unified specification;
• automatically generate a hardware design for the system based on the first and second configurations, the hardware design including the hardware-level connection between the first and second interfaces;
• and
• automatically generate a schematic for the system based on the first and second configurations, the schematic including connections between a first plurality of pins of the first interface and a second plurality of pins of the second interface.