Global routing in circuit design

A system for fabricating an integrated circuit on a wafer, comprising:

• a memory;
• and
• a processor operative to:
• receive a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets;
• generate a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets;
• calculate a sum of the number of pins;
• calculate a sum of the length of the nets;
• identify a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value;
• determine the bounding box maximum dimension of the identified net;
• calculate a tile size as a function of the bounding box maximum dimension;
• perform a global routing process using the calculated tile size to generate a global routing design;
• and
• fabricate the integrated circuit based on the global routing design.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method for fabricating an integrated circuit on a wafer, comprising:

• receiving a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets;
• generating a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets;
• calculating a sum of the number of pins;
• calculating a sum of the length of the nets;
• identifying a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value;
• determining the bounding box maximum dimension of the identified net;
• calculating a tile size as a function of the bounding box maximum dimension;
• performing a global routing process using the calculated tile size to generate a global routing design;
• and
• using the global routing design to fabricate an integrated circuit on a wafer.