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US 10,372,860 B2Granted
Netlist abstraction for circuit design floorplanning
AssigneeSynopsys, Inc.
InventorsBalkrishna R. Rashingkar, Leonardus J. van Bokhoven, Peiqing Zou
Life of this patent
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Abstract
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
Claims18
A method, comprising:
- using one or more processors of a computing system to create a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein creating the netlist abstraction comprises:
- creating a top-level netlist abstraction based on the top-level portion of the netlist;
- for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block;
- and
- retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction;
- loading the netlist abstraction into a memory of the computing system, wherein the netlist abstraction provides full-chip context of the circuit design for performing floorplanning operations;
- and
- performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design.
5 more elements
A non-transitory computer-readable storage medium storing instructions that, when executed by a computing system, cause the computing system to perform a method comprising:
- creating a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein said creating the netlist abstraction comprises:
- creating a top-level netlist abstraction based on the top-level portion of the netlist;
- for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block;
- and
- retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction;
- loading the netlist abstraction into a memory of the computing system, wherein the netlist abstraction provides full-chip context of the circuit design for performing floorplanning operations;
- and
- performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design.
5 more elements
An apparatus, comprising:
- one or more processors;
- and
- a non-transitory storage medium storing instructions that, when executed by the one or more processors, cause the apparatus to perform a method comprising:
- creating a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein said creating the netlist abstraction comprises:
- creating a top-level netlist abstraction based on a top-level portion of the netlist;
- for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block;
- and
- retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction;
- loading the netlist abstraction into a memory of the apparatus, wherein the netlist abstraction provides full-chip context of the circuit design for floorplanning operations;
- and
- performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design.
8 more elements
Dependencies are inferred from the claim text.