System and method for designing system on chip (SoC) circuits using single instruction multiple agent (SIMA) instructions

A system for designing SoC for manufacturing integrated circuit design of SoC using artificial intelligence and reinforcement learning technique, the system comprising:

• a first processor configured to create at least one reinforcement learning agent and at least one corresponding reinforcement learning environment, and wherein said first processor is further configured to assign a reinforcement learning agent ID to said reinforcement learning agent, and a reinforcement learning environment ID to said reinforcement learning environment;
• a first memory module communicably coupled to said first processor, and wherein said first memory module is configured to store an application-domain specific instruction set (ASI), SoC specification input and a chip database library, and wherein said application-domain specific instruction set comprises instructions for initializing a chip topology from the SoC specification, and wherein said the application-domain specific instruction set is further configured to create a plurality of domains and a plurality of subdomains for artificial intelligence (AI) setup to generate chip specific graph library, and wherein each of said instructions incorporates at least one of said reinforcement learning agent ID and said reinforcement learning environment ID as an operand;
• a complex instruction fetch and decode (CISFD) unit communicably coupled to said memory module configured to store an application-domain specific instruction set (ASI), SoC specification input and a chip database library, and wherein said application-domain specific instruction set comprises instructions for initializing a chip topology from the SoC specification, and wherein said application-domain specific instruction set is further configured to create a plurality of domains and a plurality of subdomains for artificial intelligence (AI) setup to generate chip specific graph library, and wherein each of said instructions incorporates at least one of said reinforcement learning agent ID and said reinforcement learning environment ID as an operand;
• a complex instruction fetch and decode (CISFD) unit communicably coupled to said memory module, and wherein said CISFD unit is configured to decode at least one of said instructions, and generate a plurality of predetermined threads corresponding to decoded instruction, and wherein said CISFD unit is still further configured to embed into the predetermined threads, at least one of said reinforcement learning agent ID and reinforcement learning environment ID associated with the decoded instruction;
• a second processor configured to initiate an interaction between the reinforcement learning agent and the reinforcement learning agent environment, and wherein said second processor comprises a plurality of cores, and wherein said second processor is configured to apply a corresponding instruction onto at least one of a reinforcement learning agent and reinforcement learning environment identified by the reinforcement learning agent ID and reinforcement learning environment ID to map each of the SoC sub domains from the plurality of SoC sub domains to a combination of environment, rewards and actions, and wherein said second processor is further configured to generate Q values for each domain using the reinforcement learning agent;
• a second memory module cooperating with said second processor, and wherein the second memory module is an on-chip memory, external DRAM, hard disk drive, and wherein the second memory module is configured to store the extracted Q values of each domain and subdomain in a hierarchical Semi Markov Decision Process (SMDP) SMDP structure in a form of SMDP Q table for optimization for planning SoC;
• and wherein the second processor is further configured to acquire optimal chip architecture for designing SoC using application-domain specific instruction set (ASI), and wherein the application-domain specific instruction set are single instruction multiple agents (SIMA) based instructions configured to map reinforcement learning environment to Electronic design automation EDA tools associated with the corresponding AI SoC subdomain, and wherein a plurality of reinforcement learnings agents are configured to interact with the reinforcement learning environment for a predefined number of times and update Q values, V values, R value, and A value in the second memory module, and wherein the acquired optimal chip architecture is used for manufacturing or fabricating an integrated circuit design of SoC.