Design-for-testability (DFT) insertion at register-transfer-level (RTL)

A method for producing a synthesized integrated circuit (IC) design that includes design-for-testability (DFT) circuitry, the method comprising:

• an IC design tool in a computer receiving a register-transfer-level (RTL) representation of an IC design that includes functional logic;
• the IC design tool in the computer adding DFT logic to the RTL representation;
• adding a set of anchor points to the RTL representation;
• electrically connecting the DFT logic with the set of anchor points;
• and
• the IC design tool in the computer performing synthesis on the RTL representation to obtain the synthesized IC design, wherein said performing synthesis on the RTL representation comprises performing a set of operations, the set of operations including:
• placing the functional logic and the DFT logic,
• electrically disconnecting the DFT logic from the set of anchor points,
• removing the set of anchor points,
• inserting and placing scan chains, and
• electrically connecting the DFT logic with the scan chains;
• and
• wherein adding the DFT logic to the RTL representation, and placing the DFT logic based on the set of anchor points improves a runtime of the IC design tool and/or a quality of results (QoR) produced by the IC design tool.

An apparatus, comprising:

• a processor;
• and
• a non-transitory computer-readable storage medium storing instructions for an integrated circuit (IC) design tool that, when executed by the processor, cause the apparatus to perform a method for producing a synthesized IC design that includes design-for-testability (DFT) circuitry, the method comprising:
• receiving a register-transfer-level (RTL) representation of an IC design that includes functional logic;
• adding DFT logic to the RTL representation;
• adding a set of anchor points to the RTL representation;
• electrically connecting the DFT logic with the set of anchor points;
• and
• performing synthesis on the RTL representation to obtain the synthesized IC design, wherein said performing synthesis on the RTL representation comprises performing a set of operations, the set of operations including:
• placing the functional logic and the DFT logic,
• electrically disconnecting the DFT logic from the set of anchor points,
• removing the set of anchor points,
• inserting and placing scan chains, and
• electrically connecting the DFT logic with the scan chains;
• and
• wherein adding the DFT logic to the RTL representation, and placing the DFT logic based on the set of anchor points improves a runtime of the IC design tool and/or a quality of results (QoR) produced by the IC design tool.