Active trace assertion based verification system

A computer-implemented method for verifying a circuit design, the computer-implemented method comprising:

• simulating, at a succession of times, the circuit design and an assertion statement for verifying the circuit design;
• evaluating a first sequence of expressions at a plurality of first evaluation times associated with the assertion statement;
• displaying, upon detection of an error in the simulated assertion, the first sequence of expressions including at least one value associated with at least one signal of the simulated circuit design;
• annotating at least one expression of the first sequence with a symbol indicating a result of evaluating the at least one expression;
• identifying at least one first variable of the first sequence that causes the error;
• marking, within the display, a first symbol associated with the identified first variable, the marking of the first symbol being distinctive relative to a marking of a second symbol of the first sequence different from the first symbol and associated with at least a second variable of the first sequence that does not cause the error;
• generating a second sequence of expressions each at a different one of a second plurality of evaluation times associated with the assertion statement, the second sequence being associated with the first variable;
• displaying the second sequence of expressions;
• identifying at least a third variable of the second sequence that causes at least one expression of the second sequence to evaluate false;
• and
• marking, within the display, a third symbol associated with the identified third variable, the marking of the third symbol being distinctive relative to a marking of a fourth symbol of the second sequence different from the third symbol and associated with at least a fourth variable of the second sequence that does not cause the second sequence to evaluate false.