Independently projecting a canonical clock

A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer cause the computer to perform the method of:

• loading a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into a computing device;
• defining at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation;
• using said computing device to perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data;
• projecting a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical;
• outputting results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design;
• determining that said performance compliance of said adjusted at least one circuit path of said at least a portion of said integrated circuit design is satisfactory;
• responsive to said determining, instantiating said adjusted at least one circuit path of said at least a portion of said integrated circuit design into a design structure;
• and
• fabricating a physical integrated circuit including a physical manifestation of said adjusted at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure.

An apparatus comprising:

• a memory;
• and
• at least one processor, coupled to said memory, and operative to:
• load a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into said memory;
• define at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation;
• perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data;
• project a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical;
• output results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design;
• determining that said performance compliance of said adjusted at least one circuit path of said at least a portion of said integrated circuit design is satisfactory;
• responsive to said determining, instantiating said adjusted at least one circuit path of said at least a portion of said integrated circuit design into a design structure;
• and
• fabricating a physical integrated circuit including a physical manifestation of said adjusted at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure.