Hardware accelerator pre-configured with coefficients for matrix-transform operations

A computing system comprising:

• a memory device configured to store an input matrix related to performing a convolution operation;
• and
• a special-purpose hardware accelerator comprising a matrix-multiplication subsystem that is pre-configured with matrix-transform coefficients for performing matrix-transform operations, wherein the matrix-multiplication subsystem is configured to perform the convolution operation by:
• reading the input matrix from the memory device;
• transforming the input matrix via matrix multiplication;
• transforming, via matrix multiplication, a parameter matrix that comprises convolution parameters for performing the convolution operation;
• applying the transformed parameter matrix to the transformed input matrix via an element-wise multiplication operation;
• and
• performing an inverse-transformation operation on the results of the element-wise multiplication operation to create an output matrix for the convolution operation.

A computer-implemented method comprising:

• reading, from a cache of a special-purpose hardware accelerator, an input matrix related to performing a convolution operation, wherein the special-purpose hardware accelerator is pre-configured with matrix-transform coefficients for performing matrix-transform operations;
• and
• performing, using the special-purpose hardware accelerator, the convolution operation by:
• transforming the input matrix via matrix multiplication;
• transforming, via matrix multiplication, a parameter matrix that comprises convolution parameters for performing the convolution operation;
• applying the transformed parameter matrix to the transformed input matrix via an element-wise multiplication operation;
• and
• performing an inverse-transformation operation on the results of the element-wise multiplication operation to create an output matrix for the convolution operation.