Data filtering using a plurality of hardware accelerators
AssigneeInternational Business Machines Corporation
InventorsSameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
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Abstract
Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
Claims20
An apparatus comprising:
- a processor;
- a memory;
- and
- a plurality of hardware accelerators;
- wherein the processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators;
- wherein the plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators;
- wherein the plurality of hardware accelerators are daisy-chain connected to one another;
- wherein each of the plurality of hardware accelerators is configured to perform a build phase and a probe phase;
- wherein build phase comprises:
- computing one or more hashes of the streamed data;
- and
- updating the at least one bit vector if the computed hashes are within a range of a corresponding partitioned portion of the at least one bit vector;
- and
- wherein the probe phase comprises:
- probing the at least one bit vector if the computed hashes are within the range of the corresponding partitioned portion of the at least one bit vector;
- generating one or more probed bit values responsive to the probing;
- and
- passing the probed bit values to a next hardware accelerator in the daisy chain;
- and
- wherein the second hardware accelerator comprises a last one of the hardware accelerators in the daisy chain, the second hardware accelerator being configured to utilize the probed bit values passed from the other ones of the plurality of hardware accelerators to determine whether to:
- (i) pass a given packet in the streamed data to the processor as part of the filtered data;
- or (ii) drop the given packet.
An apparatus comprising:
- a processor;
- a memory;
- and
- a plurality of hardware accelerators;
- wherein the processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators;
- wherein the plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators;
- wherein the plurality of hardware accelerators are daisy-chain connected to one another;
- and
- wherein each of the plurality of hardware accelerators is configured:
- to receive one or more packets each comprising a set of flags and a value, the set of flags comprising a phase flag and two or more match flags;
- and
- to perform one of a build phase and a probe phase responsive to the value of the phase flag;
- wherein the second hardware accelerator comprises a last one of the hardware accelerators in the daisy chain, the second hardware accelerator being configured to utilize values of match flags passed from the other ones of the plurality of hardware accelerators to determine whether to:
- (i) pass a given packet in the streamed data to the processor as part of the filtered data;
- or (ii) drop the given packet.
Dependencies are inferred from the claim text.