Short address mode for communicating waveform

A bus master apparatus, comprising:

• an interface circuit configured to couple the bus master apparatus to a serial bus;
• and
• a processing circuit configured to:
• detect one or more slaves on the serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address,
• calculate a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves,
• generate shortened slave addresses for the one or more slaves, respectively, wherein a length of each shortened slave address is the number of slave address bits,
• assign a generated shortened slave address to each of the one or more slaves,
• send a first indication to a slave to activate the shortened address mode,
• send the waveform to the slave via the serial bus using an assigned shortened slave address, and
• send a second indication to the slave to deactivate the shortened address mode.

A method performed at a slave coupled to a serial bus, comprising:

• indicating to a bus master that the slave supports a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address;
• receiving from the bus master an assignment of the shortened slave address, wherein a length of the shortened slave address is equivalent to a number of slave address bits needed to address in a binary form a quantity of slaves on the serial bus supporting the shortened address mode;
• receiving a first indication from the bus master to activate the shortened address mode;
• receiving the waveform from the bus master based on the assigned shortened slave address;
• and
• receiving a second indication from the bus master to deactivate the shortened address mode.

A slave device, comprising:

• an interface circuit configured to couple the slave device to a serial bus;
• and
• a processing circuit configured to:
• indicate to a bus master that the slave device supports a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address;
• receive from the bus master an assignment of the shortened slave address, wherein a length of the shortened slave address is equivalent to a number of slave address bits needed to address in a binary form a quantity of slaves on the serial bus supporting the shortened address mode;
• receive a first indication from the bus master to activate the shortened address mode;
• receive the waveform from the bus master based on the assigned shortened slave address;
• and
• receive a second indication from the bus master to deactivate the shortened address mode.