Bimodal PHY for low latency in high speed interconnects

A Physical layer (PHY) chip, configured to interface with a Media Access Control layer (MAC) block, comprising:

• a PHY block including circuitry to implement a Physical layer;
• and
• a PHY/MAC interface including,
• a low pin count Physical Interface for PCI Express (PIPE) interface comprising,
• means for coupling the PHY block chip to a small number of wires to transmit signals to and receive signals from the MAC block;
• and
• one or more PHY PIPE registers,
• wherein the low pin count PIPE interface is configured to transfer register commands to the MAC block and receive register commands from the MAC block over the small number of wires in a time-multiplexed manner.

A Media Access Control layer (MAC) block, configured to interface with a Physical layer (PHY) block, comprising:

• means for implementing a MAC layer;
• and
• a PHY/MAC interface including,
• a low pin count Physical Interface for PCI Express (PIPE) interface comprising,
• means for coupling the MAC block to a small number of wires to transmit signals to and receive signals from the PHY block;
• and
• one or more MAC PIPE registers,
• wherein the low pin count PIPE interface is configured to transfer register commands to the PHY block and receive register commands from the PHY block over the small number of wires in a time-multiplexed manner.