Apparatuses for providing data received by a state machine engine
AssigneeMicron Technology, Inc.
InventorsDavid R. Brown, Harold B Noyes, Inderjit S. Bains
Life of this patent
Estimating the term…
Abstract
An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
Claims22
A system comprising:
- a processor;
- and
- a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups, wherein the inter-rank bus enables each state machine engine of the rank to receive an assigned portion of a data stream to be analyzed when the rank is configured as multiple logical groups.
A system comprising:
- a processor;
- and
- a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups,
- wherein the processor is configured to assign a number to each state machine engine of the rank,
- wherein the rank of state machine engines comprises a module including the rank, and
- wherein the processor is configured to assign the number during initialization of the module.
A system comprising:
- a processor;
- and
- a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups, wherein the processor is configured to provide data to a particular state machine engine of the rank to configure the particular state machine engine as a master device.
A system comprising:
- a processor;
- and
- a rank of state machine engines configured as one logical group, wherein the state machine engines of the rank are coupled together by an inter-rank bus, each state machine engine of the rank being configured to:
- store a respective portion of data received at an interface;
- provide the respective portion of data to the inter-rank bus in a data burst;
- and
- analyze all of the portions of data provided to the inter-rank bus by the state machine engines of the rank during the data burst.
A system comprising:
- a processor;
- and
- a rank of state machine engines configured as multiple logical groups, wherein the state machine engines of the rank are coupled together by an inter-rank bus, each state machine engine of the rank being configured to:
- store respective portions of data received at an interface;
- provide the respective portions of data to the inter-rank bus in a data burst;
- and
- analyze portions of data provided on the inter-rank bus that correspond to the logical group to which the respective state machine engine belongs.
Dependencies are inferred from the claim text.