Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system

A system, comprising:

• a processor;
• one or more Direct Memory Access (DMA) engines;
• and
• a data transfer resource, wherein the data transfer resource is:
• coupled to the processor and to each of the one or more DMA engines;
• and
• configured to perform DMA operations, comprising:
• identifying one or more predicate data transfers associated with the one or more DMA engines, wherein a predicate data transfer comprises a data transfer associated with a dependent data transfer and wherein completion of the dependent data transfer depends on completion of the predicate data transfer;
• maintaining data transfer completion (DTC) information, wherein the DTC information includes one or more DTC bits corresponding to the one or more predicate data transfers and wherein a DTC bit indicates a completion status of a corresponding predicate data transfer;
• and
• providing at least a portion of the DTC information to at least one of the one or more DMA engines.

An article of manufacture, comprising:

• a non-transient computer-readable medium having stored thereon processor-executable instructions that, when executed by a processor, cause the processor to perform a direct memory access (DMA) method comprising:
• identifying one or more dependent data transfers associated with one or more DMA engines;
• maintaining data transfer completion (DTC) information indicative of a completion status of one or more predicate data transfers, wherein the DTC information includes a DTC bit corresponding to each of the one or more predicate data transfers and wherein a dependent data transfer comprises a data transfer dependent on completion of a predicate data transfer;
• responsive to detecting execution of a first dependent data transfer, wherein the first dependent data transfer depends on completion of a first predicate data transfer, monitoring the DTC bit corresponding to the first predicate data transfer;
• and
• responsive to detecting completion of the first predicate data transfer, updating the DTC bit corresponding to the first predicate data transfer.