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US 10,372,621 B2Granted
Mechanism to support variable size page translations
AssigneeIntel Corporation
InventorsNiranjan L. Cooray, Altug Koker, Nicolas Kacevas, Parth S. Damani, David Standring
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Abstract
An apparatus to facilitate page translation is disclosed. The apparatus a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations and a page size table (PST) including a plurality of entries to store page size corresponding to each of the TLB entries.
Claims17
An apparatus to facilitate page translations, comprising:
- a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations;
- a page size table (PST) including a plurality of entries to store a page size corresponding to each of the TLB entries, wherein an entry is allocated in the PST at the time the TLB entry is allocated;
- and
- a translation component to search the PST in response to receiving a request to translate a page to determine a size of the page, search the TLB for the page translation using an adjusted virtual address upon determining the size of the page from the PST and discard the PST entry and the adjusted virtual address upon determining a TLB miss.
1 more element
A method to facilitate page translations, comprising:
- receiving a page translation request for a virtual address;
- searching a page size table (PST) including a plurality of entries to determine a size of a page;
- searching a set associative translation lookaside buffer (TLB) including a plurality of entries for a physical page translation upon determining the page size;
- determining whether a hit has occurred at the PST;
- determining whether an entry in the PST has a second page size upon determining that a hit has occurred at the PST;
- and
- returning the second page size upon determining that the entry in the PST has the second page size.
4 more elements
A system to facilitate page translations, comprising:
- a memory;
- and
- a memory management unit (MMU) coupled to the memory, including:
- a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations;
- and
- a page size table (PST) including a plurality of entries to store a page size corresponding to each of the TLB entries, wherein an entry is allocated in the PST at the time the TLB entry is allocated;
- and
- a translation component to search the PST in response to receiving a request to translate a page to determine a size of the page search the TLB for the page translation using an adjusted virtual address upon determining the size of the page from the PST and discard the PST entry and the adjusted virtual address upon determining a TLB miss.
5 more elements
Dependencies are inferred from the claim text.