Data backup method, data recovery method and storage controller

A data recovery method, adapted to a storage device having a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical units, and the rewritable non-volatile memory module is configured with a plurality of physical addresses, wherein a plurality of logical addresses are configured to a host system coupled to the storage device, the data recovery method comprising:

• loading a latest first logical-to-physical table stored in the rewritable non-volatile memory module to a memory to form a second logical-to-physical table, wherein the first logical-to-physical table and the second logical-to-physical table all record a plurality of first physical addresses, among the physical addresses, respectively corresponding to the logical addresses, wherein the first logical-to-physical table only comprises the first physical addresses respectively corresponding to the logical addresses, and the first logical-to-physical table does not comprise any trim mark;
• updating the second logical-to-physical table according to physical addresses of valid data of which a writing time is later than the first logical-to-physical table in the rewritable non-volatile memory module and corresponding logical addresses;
• and
• recording a plurality of trim marks to the second logical-to-physical table to make the trim marks respectively correspond to the logical addresses of the second logical-to-physical table, wherein a preset value of the trim marks is a first bit value.

A storage controller, used for controlling a storage device having a rewritable non-volatile memory module, the storage controller comprising:

• a connection interface circuit, coupled to a host system, wherein a plurality of logical addresses are configured to the host system;
• a memory interface control circuit, coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical units, and the rewritable non-volatile memory module is configured with a plurality of physical addresses;
• and
• a processor, coupled to the connection interface circuit and the memory interface control circuit,
• wherein the processor maintains a first logical-to-physical table in a memory, wherein the first logical-to-physical table records a plurality of first trim marks respectively corresponding to a plurality of first logical addresses and a plurality of first physical addresses, among the physical addresses, respectively corresponding to the first logical addresses, wherein a preset value of the first trim marks is a first bit value,
• wherein the processor receives a trim command from the host system, wherein the trim command indicates that first data stored in a logical address section is invalid, wherein the logical address section comprises one or more second logical addresses,
• wherein the processor does not clear second physical addresses, among the first physical addresses of the first logical-to-physical table, respectively corresponding to the one or more the second logical addresses according to the trim command, and changes second trim marks, among the first trim marks, respectively corresponding to the one or more second logical addresses to a second bit value,
• wherein when a predetermined condition is met, the processor updates the first logical-to-physical table according to the first trim marks, and stores a second logical-to-physical table to the rewritable non-volatile memory module according to the updated first logical-to-physical table, wherein the second logical-to-physical table only includes the first physical addresses respectively corresponding to the first logical addresses of the updated first logical-to-physical table, and does not include the first trim marks.

A storage controller, used for controlling a storage device having a rewritable non-volatile memory module, the storage controller comprising:

• a connection interface circuit, coupled to a host system, wherein a plurality of logical addresses are configured to the host system;
• a memory interface control circuit, coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical units, and the rewritable non-volatile memory module is configured with a plurality of physical addresses;
• and
• a processor, coupled to the connection interface circuit and the memory interface control circuit,
• wherein the processor loads a latest first logical-to-physical table stored in the rewritable non-volatile memory module to a memory to form a second logical-to-physical table, wherein the first logical-to-physical table and the second logical-to-physical table all record a plurality of first physical addresses, among the physical addresses, respectively corresponding to the logical addresses, wherein the first logical-to-physical table only comprises the first physical addresses respectively corresponding to the logical addresses, and the first logical-to-physical table does not comprise any trim mark,
• wherein the processor updates the second logical-to-physical table according to physical addresses of valid data of which a writing time is later than the first logical-to-physical table in the rewritable non-volatile memory module and corresponding logical addresses,
• the processor further records a plurality of trim marks to the second logical-to-physical table to make the trim marks respectively correspond to the logical addresses of the second logical-to-physical table, wherein a preset value of the trim marks is a first bit value.