Apparatus and method for maintaining address translation data within an address translation cache

An apparatus comprising:

• an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system;
• control circuitry to perform an allocation process to determine the address translation data to be stored in each entry;
• the address translation cache arranged to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk, said plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address;
• and
• the control circuitry arranged, when performing the allocation process, to apply an allocation policy that permits each of the entries to be used for any of said plurality of different types of address translation data, and to store type identification data in association with each entry to enable the type of the address translation data stored therein to be determined;
• wherein:
• each entry has virtual address data associated therewith;
• the control circuitry is responsive to a received virtual address, to perform a lookup process to determine with reference to the virtual address data of at least a subset of the entries whether a hit condition is detected;
• the address translation cache is a fully associative cache;
• for each entry, the control circuitry is arranged to identify a page size of a page within the memory system that is associated with the address translation data stored in that entry, and to determine from said size a subset of the received virtual address bits to be compared with corresponding bits of the virtual address data;
• and
• the control circuitry is arranged to detect the hit condition in dependence on whether said subset of the received virtual address bits match the corresponding bits of the virtual address data.

An apparatus comprising:

• an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system;
• control circuitry to perform an allocation process to determine the address translation data to be stored in each entry;
• the address translation cache arranged to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk, said plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address;
• and
• the control circuitry arranged, when performing the allocation process, to apply an allocation policy that permits each of the entries to be used for any of said plurality of different types of address translation data, and to store type identification data in association with each entry to enable the type of the address translation data stored therein to be determined;
• wherein:
• each entry has virtual address data associated therewith;
• the control circuitry is responsive to a received virtual address, to perform a lookup process to determine with reference to the virtual address data of at least a subset of the entries whether a hit condition is detected;
• the address translation cache is a set associative cache;
• the control circuitry is arranged to implement the lookup process by performing a sequence of lookup operations, each lookup operation having an associated type, the associated type comprising at least an associated page size;
• for each lookup operation the control circuitry is arranged to select a first subset of the received virtual address bits in dependence on the associated page size, and to use said first subset of the received virtual address bits as an index to identify a set within the set associative cache;
• the control circuitry is further arranged to identify in dependence on the associated page size a second subset of the received virtual address bits to be compared with corresponding bits of the virtual address data;
• and
• the control circuitry is arranged to detect the hit condition during performance of the lookup operation when said second subset of the received virtual address bits match the corresponding bits of the virtual address data within an entry of the identified set and the type identification data for that entry matches the associated type for the lookup operation.

A method of maintaining address translation data within an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system, the method comprising:

• performing an allocation process to determine the address translation data to be stored in each entry;
• storing within the address translation cache address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk, said plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address;
• and
• when performing the allocation process, applying an allocation policy that permits each of the entries to be used for any of said plurality of different types of address translation data, and storing type identification data in association with each entry to enable the type of the address translation data stored therein to be determined;
• wherein each entry has virtual address data associated therewith, and the method further comprises:
• performing, in response to a received virtual address, a lookup process to determine with reference to the virtual address data of at least a subset of the entries whether a hit condition is detected;
• and
• selecting, in the presence of the hit condition being detected for multiple entries, one of the multiple entries whose address translation data represents a most complete address translation for the received virtual address.