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US 10,372,612 B2Granted
Apparatuses and methods for compute enabled cache
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
Claims20
An apparatus, comprising:
- a memory configured to store cache data and having:
- a memory array;
- a sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations;
- and
- a controller coupled to the memory array, the controller configured to:
- create a block select as metadata to a cache line to control alignment of cache blocks within the memory array;
- and
- create a subrow select as metadata to the cache line to control placement of the cache line on a particular row in the memory array to align the cache line to one or more of the plurality of sense amplifiers.
5 more elements
An apparatus, comprising:
- a memory device comprising:
- an array of memory cells;
- sensing circuitry coupled to the array;
- and
- a controller coupled to the array and sensing circuitry and configured to:
- receive a cache line having block select and subrow select metadata;
- and
- operate on the block select and subrow select metadata to:
- control alignment of cache blocks in the array;
- and
- allow the cache line to be placed on a particular row of the array to align the cache line to the sensing circuitry.
8 more elements
A method for operating a cache memory, comprising:
- creating a block select as metadata to a cache line to control alignment of cache blocks in a memory array of the cache memory comprising sensing circuitry including a plurality of sense amplifiers and a plurality of compute components to perform logical operations;
- and
- creating a subrow select as metadata to the cache line to control placement of at least a portion of the cache line on multiple rows in the memory array.
Dependencies are inferred from the claim text.