Fast cache warm-up
AssigneeIntel Corporation
InventorSagi Weiss
Life of this patent
Estimating the term…
Abstract
An embodiment of a semiconductor package apparatus may include technology to determine if a memory request for a second level memory results in a miss with respect to a first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten, if the memory request results in the miss with respect to the first level memory, and blank a corresponding range of the first level memory if the range of the second level memory corresponding to the memory request is determined to be unwritten. Other embodiments are disclosed and claimed.
Claims24
An electronic processing system, comprising:
- a processor;
- a multi-level memory communicatively coupled to the processor, the multi-level memory including a first level memory and a second level memory;
- and
- logic communicatively coupled to the processor and the multi-level memory to:
- determine if a memory request for the second level memory results in a miss with respect to the first level memory,
- determine if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory, and
- blank a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten.
A semiconductor package apparatus, comprising:
- a substrate;
- and
- logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to:
- determine if a memory request for a second level memory results in a miss with respect to a first level memory,
- determine if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory, and
- blank a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten.
A method of controlling a memory, comprising:
- determining if a memory request for a second level memory results in a miss with respect to a first level memory;
- determining if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory;
- and
- blanking a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten.
A method of controlling a memory, comprising:
- determining if a memory request for a second level memory results in a miss with respect to a first level memory;
- determining if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory;
- and
- blanking a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten.
Dependencies are inferred from the claim text.