Ordering updates for nonvolatile memory accesses

A method for ordering updates for nonvolatile memory accesses, the method comprising:

• receiving, by a write ordering buffer, a first update of a plurality of updates that is propagated from a write-through processor cache of a processor, wherein the first update is associated with a first epoch;
• storing the first update in a first buffer entry of a plurality of buffer entries of the write ordering buffer;
• receiving a second update of the plurality of updates that is propagated from the write-through processor cache, wherein the second update is associated with a second epoch;
• allocating a second buffer entry of the plurality of buffer entries, wherein the second update is stored in the second buffer entry;
• in response to determining that the second update is less than the cache line size, updating a dirty bit associated with the second buffer entry to specify that the second buffer entry is dirty;
• evicting the first buffer entry and the second buffer entry to non-volatile memory in a first in first out order;
• receiving a third update of the plurality of updates that is propagated from the write-through processor cache, wherein the third update is associated with a second epoch;
• and
• coalescing the third update into the second buffer entry.

A non-transitory machine-readable storage medium encoded with instructions executable by a processor for ordering updates for nonvolatile memory accesses, the machine-readable storage medium comprising instructions to:

• receive a first update of a plurality of updates that is propagated from a write-through processor cache of a processor, wherein the first update is associated with a first epoch;
• in response to determining that a write ordering buffer includes a first buffer that is associated with the first epoch, store the first update in the first buffer entry of a plurality of buffer entries;
• receive a second update of the plurality of updates that is propagated from the write-through processor cache, wherein the second update is associated with a second epoch;
• allocate a second buffer entry of the plurality of buffer entries, wherein the second update is stored in the second buffer entry;
• to in response to determining that the second update is less than the cache line size, update a dirty bit associated with the second buffer entry to specify that the second buffer entry is dirty;
• evict the first buffer entry and the second buffer entry to non-volatile memory in epoch order;
• and
• receive a third update of the plurality of updates that is propagated from the write-through processor cache, wherein the third update is associated with a second epoch;
• and
• coalesce the third update into the second buffer entry.