FPGA mismatched packet stop for a safety system

A method for fault-tolerant failsafe computer comprising:

• receiving a first data packet and generating a second data packet based on a copy of the first data packet;
• generating a first key based on a comparison between the first data packet and a copy of the second data packet and determining whether the first key and a second key are valid keys;
• generating the second key based on a comparison between the second data packet and a copy of the first data packet;
• and
• in response to the determination of whether the first key and the second key are valid keys, generating an outgoing data packet based on the first data packet.

A fault-tolerant failsafe computer voting system comprising:

• a switch module that receives a first data packet and generates a second data packet based on a copy of the first data packet;
• a first voting module that generates a first key based on a comparison between the first data packet and a copy of the second data packet and that determines whether the first key and a second key are valid keys;
• a second voting module that generates the second key based on a comparison between the second data packet and a copy of the first data packet;
• and
• a processing module that, in response to determining whether the first key and the second key are valid keys, generates an outgoing data packet based on the first data packet.