Apparatus including refresh controller controlling refresh operation responsive to data error

A device comprising:

• a memory cell array device including first and second memory cell arrays, the first memory cell array comprising a plurality of first memory cells configured to store user data, the second memory cell array comprising a plurality of second memory cells configured to store verification data relating to the user data;
• a verification circuit configured to receive the user data from the first memory cell array, to receive the verification data from the second memory cell array, to check whether the user data includes an error, by using the verification data, and to provide, when the user data includes the error, an error signal;
• and
• a refresh control circuit configured to:
• execute a refresh operation on the first memory cell array in order to increase a frequency of the refresh operation on a memory cell storing the error, wherein the refresh control circuit comprises an address register configured to receive, from the verification circuit, the error signal, wherein the address register is further configured to provide an address corresponding to the memory cell storing the error, wherein the refresh control circuit comprises a comparison circuit configured to receive the address, and to compare a portion of the address with a portion of an address of the plurality of first memory cells, wherein the portion of the address corresponding to the memory cell storing the error is less than all of the address corresponding to the memory cell storing the error, and wherein the portion of the address is less than all of the address,
• activate a detection signal when the portion of the address corresponding to the memory cell storing the error is determined to be a matched error address based on a match between the portion of the address and the portion of the address of the plurality of first memory cells, and
• output, to the memory cell array device, the matched error address, based on the activated detection signal, and
• wherein the refresh operation is performed while a refresh counter completes a round of count value.

A device comprising:

• a plurality of word lines each coupled to a plurality of memory cells on which a refresh operation is performed in order to retain information stored therein;
• a refresh control circuit configured to control the refresh operation;
• and
• a verification circuit configured to receive data on at least first and second word lines among the plurality of word lines, to check the data on the at least first and second word lines among the plurality of word lines, and to provide, when the received data includes the error, an error signal,
• wherein the refresh control circuit is configured to receive the error signal,
• wherein, responsive to a comparison of a portion of an error address provided based on the received error signal with a portion of an address of the plurality of memory cells, the refresh control circuit is configured to change a frequency of the refresh operation on the first word line to a first frequency by outputting, from the verification circuit and at the first frequency, the error address that has the portion determined to match the portion of the address of the plurality of memory cells,
• wherein the portion of the error address is less than all of the error address and the portion of the address of the plurality of memory cells is less than all of the address of the plurality of memory cells, and
• wherein the error address output at the first frequency is associated with the first word line, and the refresh control circuit is further configured to keep a frequency of the refresh operation on the second word line which is clear from an error at a second frequency, and to perform a refresh operation while a refresh counter completes one round of count value updating.