Compute architecture in a memory device of distributed computing system

A processing module embedded in a memory device, the processing module configured to execute instructions implementing the following method:

• receiving at least one partial task related to a group of slices of contiguous data;
• receiving slices of the group of slices of contiguous data to produce received slices;
• random access storing received slices in the memory device;
• determining whether to execute the at least one partial task;
• in response to a positive determination:
• random access retrieving a portion of the received slices from the memory device;
• executing the at least one partial task using the portion of the received slices to generate a partial result;
• random access storing the partial result in the same memory device used to store the received slices;
• dispersed storage error encoding the partial result to produce a plurality of sets of dispersed error encoded slices;
• and
• facilitating, by the processing module, dispersed storage of the plurality of sets of dispersed error encoded slices in a distributed storage task network (DSTN).

A solid state memory device comprising:

• solid state random access storage circuitry;
• and
• a processor coupled to the solid state random access storage circuitry, the processor configured to:
• receive a task related to a group of slices of contiguous data;
• receive slices of the group of slices of contiguous data to produce received slices;
• store received slices in the solid state random access storage circuitry;
• determine whether to execute the task;
• in response to a positive determination:
• retrieve a portion of the received slices from the solid state random access storage circuitry;
• execute the task on the portion of the received slices to generate a partial result;
• store the partial result in the same solid state random access storage circuitry used to store the received slices;
• dispersed storage error encoding the partial result to produce a plurality of sets of dispersed error encoded slices;
• and
• facilitate dispersed storage of the plurality of sets of dispersed error encoded slices in a distributed storage task network (DSTN) memory, at least partially outside of the random access storage circuitry.