Register allocation system

A method, comprising:

• storing, at a free list circuit, a free list that identifies unallocated registers within a register file having a plurality of regions, wherein the plurality of regions includes a first region of registers controlled by a first region gating circuit and a second region of registers controlled by a second region gating circuit;
• receiving, at the free list circuit, a request to identify multiple unallocated registers;
• identifying, in parallel by the free list circuit, a plurality of unallocated registers, wherein the identifying includes using a mapping between registers identified by the free list and registers of the register file, and wherein the mapping is implemented in manner that causes the free list circuit to identify unallocated registers in the first region for allocation before identifying unallocated registers in the second region for allocation based on an expected search pattern of the free list;
• and
• preventing, by one or more region gating circuits, one or more respective clock signals from being provided to one or more of the plurality of regions during a register access corresponding to the request to identify multiple unallocated registers, wherein the one or more regions do not include allocated registers.

An integrated circuit, comprising:

• a register file having a first region of registers and a second region of registers;
• a plurality of clock gating circuits including a first gating circuit and a second gating circuit, wherein a first gating circuit is configured to control a clock signal provided to the first region, wherein a second gating circuit is configured to control a clock signal provided to the second region;
• a free list circuit configured to:
• store a free list that identifies unallocated registers of the register file;
• and
• in response to one or more outstanding requests to identify multiple unallocated registers, perform multiple search operations on different portions of the free list in parallel;
• and
• a register allocation adjustment circuit configured to implement a mapping between registers identified by the free list circuit and registers of the register file, wherein the mapping is implemented in a manner that causes the free list circuit, during performance of the multiple searches, to identify unallocated registers of the first region prior to identifying unallocated registers of the second region.