Method and apparatus for a self-clocked, event triggered superscalar processor

A processor comprising:

• a plurality of parallel self-timed function units;
• an instruction dispatcher configured to dispatch one or more instructions to one or more of the function units in a program counter order, the instruction dispatcher further configured to tag at least one of the one or more instructions with a dependent function unit identifier configured to identify a particular function unit for execution of a subsequent instruction;
• and
• a plurality of event logic circuits, each of the plurality of event logic circuits being associated with a function unit of the plurality of function units, each event logic circuit being configured to trigger operation of the function unit to generate an instruction execution result in response to receiving, at the function unit, a dispatched instruction;
• wherein at least one of the execution results is generated in an order different from the program counter order, and
• wherein the execution result generated by the instruction tagged with the dependent function unit identifier is used as an operand by the particular function unit identified by the dependent function unit identifier in execution of the subsequent instruction.