Tensor processor instruction set architecture
AssigneeMicrosoft Technology Licensing, LLC
InventorsJeremy Halden Fowers, Kalin Ovtcharov, Steven Karl Reinhardt, Eric Sen Chung, Ming Gang Liu
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AssigneeMicrosoft Technology Licensing, LLC
InventorsJeremy Halden Fowers, Kalin Ovtcharov, Steven Karl Reinhardt, Eric Sen Chung, Ming Gang Liu
Estimating the term…
A hardware accelerator having an efficient instruction set is disclosed. An apparatus may comprise logic configured to access a first and a second machine instruction. The second machine instruction may be missing a tensor operand needed to execute the second machine instruction. The logic may be further configured to execute the first machine instruction, resulting in a tensor. The logic may be further configured to execute the second machine instruction using the resultant tensor as the missing tensor operand.
An apparatus comprising:
A method of executing machine instructions in a tensor processor, comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.