US 10,372,455 B2Granted

Hand held device to perform a bit range isolation instruction

AssigneeIntel Corporation

InventorsMaxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal

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Abstract

Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

Claims19

Dependent claims

A hand held device comprising:

a dynamic random access memory;
a memory controller coupled to the dynamic random access memory;
a flash memory device to store data;
a wireless transceiver;
a user input device;
a network controller to couple the hand held device to a network;
a shared cache to store data;
and
a plurality of processor cores coupled to the memory controller and the shared cache, at least one of the plurality of processor cores comprising:
an L1 cache;
an instruction fetch logic;
branch prediction logic;
a plurality of registers including control registers, status registers, and 64-bit general purpose registers, wherein a lower 32-bits of the 64-bit general purpose registers are addressable to operate on 32-bit operands, and wherein the status registers include a 32-bit register that is to have a plurality of bits associated with a group of status flags, the status flags to include a carry flag, a zero flag, a sign flag, and an overflow flag;
an instruction decoder to receive and decode a bit range isolation instruction, the instruction to implicitly indicate a first end of a range of bits of interest, and, through an immediate associated with the instruction, to explicitly specify as a bit position a second end of the range of bits of interest;
and
an execution unit to perform a bit range isolation operation on a source operand of the bit range isolation instruction, the source operand to be stored in one of the 64-bit general purpose registers, an encoding of the bit range isolation instruction to indicate one of a plurality of source operand sizes, including a 32-bit operand size and a 64-bit operand size, the execution unit comprising:
mask generation logic to generate a mask;
and
bitwise operation logic to receive the source operand and the mask, and to perform a bitwise operation on the source operand and the mask to produce a result that is to include a first range of bits in which each bit is to be identical in value to a bit of the source operand in a corresponding position, and a second range of bits more significant than the first range that are all to have a same value regardless of bit values in corresponding positions of the source operand,
wherein it is implicit to the bit range isolation instruction that the first range of bits of the result is not moved in bit position relative to the bits of the identical values of the source operand,
wherein it is implicit to the bit range isolation instruction that the second range of bits are all to have the same value, and
wherein the instruction allows the same value to be binary one.

19 more elements

A hand held device comprising:

a dynamic random access memory;
a memory controller coupled to the dynamic random access memory;
a flash memory device to store data;
a wireless transceiver;
a user input device;
a network controller to couple the hand held device to a network;
a shared cache to store data;
and
a plurality of processor cores coupled to the memory controller and the shared cache, at least one of the plurality of processor cores comprising:
an L1 cache;
an instruction fetch logic;
branch prediction logic;
a plurality of registers including control registers, status registers, and 64-bit general purpose registers, wherein a lower 32-bits of the 64-bit general purpose registers are addressable to operate on 32-bit operands, and wherein the status registers include a 32-bit register that is to have a plurality of bits associated with a group of status flags, the status flags to include a carry flag, a zero flag, a sign flag, and an overflow flag;
an instruction decoder to receive and decode a bit range isolation instruction, the instruction to inflexibly indicate a first end of a range of bits of interest, and, through an immediate associated with the instruction, to explicitly specify as a bit position a second end of the range of bits of interest;
and
an execution unit to perform a bit range isolation operation on a source operand of the bit range isolation instruction, the source operand to be stored in one of the 64-bit general purpose registers, an encoding of the bit range isolation instruction to indicate one of a plurality of source operand sizes, including a 32-bit operand size and a 64-bit operand size, the execution unit comprising:
mask generation logic to generate a mask;
and
bitwise operation logic to receive the source operand and the mask, and to perform a bitwise operation on the source operand and the mask to produce a result that is to include a first range of bits in which each bit is to be identical in value to a bit of the source operand in a corresponding position, and a second range of bits more significant than the first range that are all to have a same value regardless of bit values in corresponding positions of the source operand,
wherein the bit range isolation instruction does not explicitly specify a start bit position where a start of the first range of bits is to be stored in the result.

17 more elements

A hand held device comprising:

a dynamic random access memory;
a memory controller coupled to the dynamic random access memory;
a flash memory device to store data;
a wireless transceiver;
a user input device;
a network controller to couple the hand held device to a network;
a shared cache to store data;
and
a plurality of processor cores coupled to the memory controller and the shared cache, at least one of the plurality of processor cores comprising:
an L1 cache;
an instruction fetch logic;
branch prediction logic;
a plurality of registers including control registers, status registers, and 64-bit general purpose registers, wherein a lower 32-bits of the 64-bit general purpose registers are addressable to operate on 32-bit operands, and wherein the status registers include a 32-bit register that is to have a plurality of bits associated with a group of status flags, the status flags to include a carry flag, a zero flag, a sign flag, and an overflow flag;
an instruction decoder to receive and decode a bit range isolation instruction, the instruction to require a particular first end of a range of bits of interest, and, through an immediate associated with the instruction, to explicitly specify as a bit position a second end of the range of bits of interest;
and
an execution unit to perform a bit range isolation operation on a source operand of the bit range isolation instruction, the source operand to be stored in one of the 64-bit general purpose registers, an encoding of the bit range isolation instruction to indicate one of a plurality of source operand sizes, including a 32-bit operand size and a 64-bit operand size, the execution unit comprising:
mask generation logic to generate a mask;
and
bitwise operation logic to receive the source operand and the mask, and to perform a bitwise AND operation on the source operand and the mask to produce a result that is to include a first range of bits in which each bit is to be identical in value to a bit of the source operand in a corresponding position, and a second range of bits more significant than the first range that are all to have a same value regardless of bit values in corresponding positions of the source operand,
wherein the instruction requires that the first range of bits of the result is to be stored starting at a least significant bit of the result, and
wherein execution of the bit range isolation instruction is to complete without shifting the first range of bits of the result.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/568,812Filed 12 Dec 2014 · continuation
Priority: 22 Dec 2009
Published: US 2015/0143084 A121 May 2015
Granted: 6 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30018
To perform operations on data operands: bit or string instructions
G06F 9/30029
To perform operations on data operands: logical and Boolean instructions, e.g. XOR, NOT
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask

Family

Application12/645,307Parent of this continuation · filed 22 Dec 2009
US 2015/0143084 A1Pre-grant publication · published 21 May 2015
US 9,003,170 B2Parent of this continuation
US 2011/0153997 A1Published application
US 10,372,455 B2This patent

From the US filing history. Foreign family members aren’t listed.

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