Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines

In a microprocessor, a method for allocation of a segmented interconnect in an integrated circuit, the method comprising:

• receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources store data for supporting execution of multiple code sequences;
• contending for the plurality of resources in accordance with the plurality of requests from the plurality of resource consumers;
• and
• accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses and a plurality of locally connected engine to engine buses,
• wherein the plurality of requests contend for a bus in the plurality of global segment buses using one or more parallel adders, wherein the one or more parallel adders assigns a segment bus to a request in the plurality of global segment buses based on a sum produced by the one or more parallel adders, and
• wherein each segment bus in the plurality of global segment buses is associated with an identifier and the sum produced by the one or more parallel adders is a sum of the current request and all preceding requests and corresponds to the identifier of the bus in the plurality of global segment buses assigned to the request.

A microprocessor, comprising:

• a plurality of resources storing data for supporting execution of multiple code sequences;
• a plurality of partitionable engines for implementing the execution of the multiple code sequences;
• a plurality of resource consumers within each of the plurality of partitionable engines;
• and
• a global interconnect structure for coupling the plurality of resource consumers with the plurality of resources to access the data and execute the multiple code sequences, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses,
• wherein the plurality of requests contend for a bus in the plurality of global segment buses using one or more parallel adders, wherein the one or more parallel adders assigns a segment bus to a request in the plurality of global segment buses based on a sum produced by the one or more parallel adders, and
• wherein each segment bus in the plurality of global segment buses is associated with an identifier and the sum produced by the one or more parallel adders is a sum of the current request and all preceding requests and corresponds to the identifier of the bus in the plurality of global segment buses assigned to the request.