Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
AssigneeIntel Corporation
InventorsVictor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara Baghsorkhi, Nalini Vasudevan
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Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
Claims20
A method of performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction that includes at least a source writemask register operand, a destination writemask register operand, and an opcode, the method comprising:
- decoding the single instruction;
- executing the decoded single instruction to determine a least significant bit position of the source writemask register that is a true value;
- storing a true value only in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position.
An article of manufacture comprising:
- a non-transitory tangible machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operand a writemask register and specifies as its destination a single writemask register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause a determination of a least significant bit position of the source writemask register that is a true value and storage of a true only value in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position.
An apparatus comprising;
- a hardware decoder to decode a generation of a predicate mask based on vector comparison instruction that includes at least a source writemask register operand, a destination writemask register operand, and an opcode;
- execution circuitry to determine a least significant bit position of the source writemask register that is a true value and store a true value only in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position.
Dependencies are inferred from the claim text.