Packed data operation mask concatenation processors, methods, systems, and instructions

A processor comprising:

• a set of packed data registers;
• a set of general-purpose registers;
• a set of packed data operation mask registers;
• a decode unit to decode an instruction that is to specify a first packed data operation mask register of the set of packed data operation mask registers, that is to specify a second packed data operation mask register of the set of packed data operation mask registers, and that is to specify a third packed data operation mask register of the set of packed data operation mask registers, the first packed data operation mask register to store a first 16-bit packed data operation mask in bits [15:0], and the second packed data operation mask register to store a second 16-bit packed data operation mask in bits [15:0];
• and
• an execution unit coupled with the decode unit, and coupled with the set of packed data operation mask registers, the execution unit, in response to the decode of the instruction, to store a result in the third packed data operation mask register, the result to include the first 16-bit packed data operation mask in bits [15:0] of the third packed data operation mask register, the second 16-bit packed data operation mask in bits [31:16] of the third packed data operation mask register, and zeroes in all bits of the third packed data operation mask register more significant than bit [31] of the third packed data operation mask register, including zeroes in at least bits [63:32] of the third packed data operation mask register.

A processor comprising:

• a plurality of packed data registers each able to store at least 512-bits;
• a plurality of general-purpose registers;
• a plurality of packed data operation mask registers, wherein instructions of an instruction set of the processor are to specify packed data operation mask registers of the plurality of packed data operation mask registers to identify predicate operands to be used for predication;
• a decode unit to decode an instruction that is to specify a first packed data operation mask register of the plurality of packed data operation mask registers, that is to specify a second packed data operation mask register of the plurality of packed data operation mask registers, and that is to specify a third packed data operation mask register of the plurality of packed data operation mask registers, the first packed data operation mask register to store a first 16-bit packed data operation mask in bits [15:0], and the second packed data operation mask register to store a second 16-bit packed data operation mask in bits [15:0], wherein the first 16-bit packed data operation mask being 16-bits in size is implicit to an opcode of the instruction;
• and
• an execution unit coupled with the decode unit, and coupled with the plurality of packed data operation mask registers, the execution unit, in response to the decode of the instruction, to store a result in the third packed data operation mask register, the result to include the first 16-bit packed data operation mask in bits [15:0] of the third packed data operation mask register in which bits of the first 16-bit packed data operation mask are to be in a same order in the result as they appear in the first packed data operation mask register, the second 16-bit packed data operation mask in bits [31:16] of the third packed data operation mask register in which bits of the second 16-bit packed data operation mask are to be in a same order in the result as they appear in the second packed data operation mask register, and zeroes in all bits of the third packed data operation mask register more significant than bit [31] of the third packed data operation mask register, including zeroes in at least bits [63:32] of the third packed data operation mask register.

An apparatus comprising:

• an instruction converter to convert a first instruction of a first instruction set to a set of one or more corresponding instructions of a second different instruction set, the first instruction to have a first set of three bits to specify a first storage location that is to have a first 16-bit packed data operation mask and to have a second set of three bits to specify a second storage location that is to have a second 16-bit packed data operation mask, wherein the first 16-bit packed data operation mask having a size of 16-bits is implicit to an opcode of the first instruction;
• and
• a processor coupled with the instruction converter, the processor including a plurality of packed data registers, a plurality of general-purpose registers, a decode unit to decode each of the set of the one or more corresponding instructions of the second different instruction set, and the processor including one or more execution units to perform the set of the one or more corresponding instructions of the second different instruction set, the processor, due to the performance of the set of the one or more corresponding instructions of the second different instruction set, to store a result in a destination storage location of the processor, the result to include the first 16-bit packed data operation mask in bits [15:0] of the destination storage location in which bits of the first 16-bit packed data operation mask are to be in a same order in the destination storage location as they appear in the first storage location, the second 16-bit packed data operation mask in bits [31:16] of the destination storage location in which bits of the second 16-bit packed data operation mask are to be in a same order in the destination storage location as they appear in the second storage location, and zeroes in all bits of the destination storage location more significant than bit [31] of the destination storage location, including zeroes in at least bits [63:32] of the destination storage location.