Multiply-add operations of binary numbers in an arithmetic unit

An arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers, comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operation, each arithmetic unit comprising at least:

• a multiplier connected to the dataflow for the high part P, Q or the low part R, S of the multiplication operands A, C and configured to compute a product of the high parts or a product of the low parts of the multiplication operands A and C;
• a right shifter connected to the dataflow of a high part BHIGH or a low part BLOW of the addend operand B, being configured to deliver a shifted high part B′HIGH or shifted low part B′LOW of the addend operand B;
• a first adder connected to an output of the multiplier and an output of the right shifter, being configured to deliver a shifted first intermediate result or a shifted second intermediate result;
• a left shifter connected to an output of the first adder, being configured to deliver a first intermediate result or a second intermediate result;
• a second adder connected to an output of the left shifter of one arithmetic unit and to an output of a left shifter of the other arithmetic unit, wherein a carry-output of the second adder of the second arithmetic unit is connected to an input of the second adder of the first arithmetic unit;
• and
• a normalizing and rounding unit connected to an output of the left shifter and a select circuit connected to outputs of the second adder and to outputs of the normalizing and rounding unit for delivering an aligned high part result or an aligned low part result.