Internally truncated multiplier

A digital down converter (DDC), comprising:

• a mixer configured to multiply samples of a radio frequency signal with samples of a down conversion frequency, to produce an intermediate frequency signal, the mixer comprising:
• a multiplier to multiply the samples of the radio frequency signal with the samples of the down conversion frequency, the multiplier comprising:
• a partial product generation circuit configured to generate a plurality of partial products for multiplying a sample of the radio frequency signal and a sample of the down conversion frequency;
• a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some of the partial products by removing a least significant bit from the at least some of partial products, to generate truncated partial products;
• a summation circuit coupled to the truncation circuit, the summation circuit configured to sum the truncated partial products produced by the truncation circuit, to generate a multiplication product;
• and
• a bias compensation circuit coupled to the summation circuit, the bias compensation circuit configured to generate a bias compensation value based on whether the sample of the radio frequency signal and the sample of the down conversion frequency are random.

A method for multiplication, the method comprising:

• generating, by a partial product generation circuit, a plurality of partial products for a multiplier and a multiplicand;
• shortening, by a truncation circuit, at least some partial products of the plurality of partial products by removing a least significant bit from the at least some of the partial products, to generate truncated partial products;
• summing, by a summation circuit, the truncated partial products, to generate a multiplication product;
• and
• generating, by a bias compensation circuit, a bias compensation value based on whether the multiplier and the multiplicand are random.