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US 10,372,413 B2Granted
First-in-first-out buffer
AssigneeInternational Business Machines Corporation
InventorsJoerg Behrend, Markus Cebulla, Rolf Fritz, Andreas Koenig, Daniel D. Sentler
Life of this patent
Estimating the term…
Abstract
Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.
Claims15
A method for use by a sender computer device that includes a first in first out buffer (FIFO) memory and a status register, the method comprising:
- receiving, by the sender computer device, a communication data set to be communicated over a communication network to a recipient computer device;
- creating, by the sender computer device, a plurality of sequential packets collectively including data of the communication data set, with each sequential packet including a substantially equal amount of data from the communication data set;
- for each given sequential packet of the plurality of sequential packets:
- determining status information for the given sequential packet, where the status information for each given sequential packet indicates of one of the following three status types:
- valid, invalid or end of sequence,
- storing, by the sender computer device, the given sequential packet in the FIFO memory while moving previously stored sequential packets through the FIFO memory in a first in first out manner, and
- storing the status information for the given sequential packet in an associated entry of the status register while shifting register values of the status register to account for storage of the status information for the given sequential packet;
- communicating, to a receiver computer device, the status register, with the communication of the status register including information indicative of:
- (i) the receiver computer should not read at least one sequential packet in the FIFO memory having a status information in the status register indicative of an invalid status, and (ii) an interrupt handler should be disabled for processing receiving the contents of the FIFO memory;
- and
- responsive to communicating the status register, communicating contents of the FIFO memory to the receiver computer device, based, at least in part on the status information for each sequential packet in the status register;
- wherein a complete instance of the status register is embedded within unused bus bandwidth and communicated simultaneously with each stored packet of the FIFO memory.
9 more elements
A computer program product (CPP) comprising:
- a first in first out buffer (FIFO) memory;
- a status register;
- a machine readable storage device;
- and
- computer code stored on the machine readable storage device, with the computer code including instructions for causing a processor(s) set to perform operations including the following:
- receiving, by a sender computer device, a communication data set to be communicated over a communication network to a recipient computer device,
- creating, by the sender computer device, a plurality of sequential packets collectively including data of the communication data set, with each sequential packet including a substantially equal amount of data from the communication data set,
- for each given sequential packet of the plurality of sequential packets:
- determining status information for the given sequential packet, where the status information for each given sequential packet indicates of one of the following three status types:
- valid, invalid or end of sequence,
- storing, by the sender computer device, the given sequential packet in the FIFO memory while moving previously stored sequential packets through the FIFO memory in a first in first out manner, and
- storing the status information for the given sequential packet in an associated entry of the status register while shifting register values of the status register to account for storage of the status information for the given sequential packet,
- communicating, to a receiver computer device, the status register, with the communication of the status register including information indicative of:
- (i) the receiver computer should not read at least one sequential packet in the FIFO memory having a status information in the status register indicative of an invalid status, and (ii) an interrupt handler should be disabled for processing receiving the contents of the FIFO memory, and
- responsive to communicating the status register, communicating contents of the FIFO memory to the receiver computer device, based, at least in part on the status information for each sequential packet in the status register;
- wherein a complete instance of the status register is embedded within unused bus bandwidth and communicated simultaneously with each stored packet of the FIFO memory.
13 more elements
A computer system (CS) comprising:
- a first in first out buffer (FIFO) memory;
- a status register;
- a processor(s) set;
- a machine readable storage device;
- and
- computer code stored on the machine readable storage device, with the computer code including instructions for causing the processor(s) set to perform operations including the following:
- receiving, by a sender computer device, a communication data set to be communicated over a communication network to a recipient computer device,
- creating, by the sender computer device, a plurality of sequential packets collectively including data of the communication data set, with each sequential packet including a substantially equal amount of data from the communication data set,
- for each given sequential packet of the plurality of sequential packets:
- determining status information for the given sequential packet, where the status information for each given sequential packet indicates of one of the following three status types:
- valid, invalid or end of sequence,
- storing, by the sender computer device, the given sequential packet in the FIFO memory while moving previously stored sequential packets through the FIFO memory in a first in first out manner, and
- storing the status information for the given sequential packet in an associated entry of the status register while shifting register values of the status register to account for storage of the status information for the given sequential packet,
- communicating, to a receiver computer device, the status register, with the communication of the status register including information indicative of:
- (i) the receiver computer should not read at least one sequential packet in the FIFO memory having a status information in the status register indicative of an invalid status, and (ii) an interrupt handler should be disabled for processing receiving the contents of the FIFO memory, and
- responsive to communicating the status register, communicating contents of the FIFO memory to the receiver computer device, based, at least in part on the status information for each sequential packet in the status register;
- wherein a complete instance of the status register is embedded within unused bus bandwidth and communicated simultaneously with each stored packet of the FIFO memory.
14 more elements
Dependencies are inferred from the claim text.