Extensible storage system controller

A storage system controller chip comprising:

• routing circuitry comprising a host interface configured to be coupled to a host device and an extension interface configured to be coupled to a secondary controller chip, wherein a bandwidth of the host interface is greater than a bandwidth of the extension interface, and the bandwidth of the host interface is split between the storage system controller chip and the secondary controller chip, and each of the storage system controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the host interface;
• a host controller coupled to a logical interface of the routing circuitry, the host controller configured to receive a host data access command from the host device via the host interface and the logical interface of the routing circuitry, wherein the routing circuitry is configured to transfer the host data access command to the secondary controller chip via the extension interface;
• a media controller coupled to the host controller and configured to transfer data between the storage system controller chip and storage media coupled to the media controller based on the received host data access command;
• and
• processor circuitry coupled to the logical interface of the routing circuitry, the processor circuitry configured to:
• receive an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip, wherein a respective host controller of the secondary controller chip is configured to provide the indication;
• and
• instruct the host controller, in response to the received indication, to notify the host device that execution of the host data access command has been completed.

A data storage system comprising:

• a primary controller chip comprising a first host interface configured to be coupled to a host device and a first extension interface;
• first storage media coupled to the primary controller chip;
• a secondary controller chip comprising a second host interface coupled to the first extension interface of the primary controller chip, a second extension interface, and a host controller, wherein a bandwidth of the first host interface is greater than a bandwidth of the first extension interface, the bandwidth of the first host interface is split between the primary controller chip and the secondary controller chip, and each of the primary controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the first host interface;
• and
• second storage media coupled to the secondary controller chip,
• wherein the primary controller chip is configured to:
• receive a host data access command from the host device via the first host interface;
• transfer the host data access command to the secondary controller chip;
• receive an indication from the secondary controller chip that execution of the transferred host data access command has been completed for data in the second storage media;
• and
• notify the host device, in response to the received indication, that execution of the host data access command has been completed, and
• wherein the secondary controller chip is configured to:
• receive the host data access command from the primary controller chip;
• execute the host data access command for the data in the second storage media;
• and
• notify, utilizing the host controller, the primary controller chip that the host data access command has been completed.

A storage system controller comprising:

• means for receiving a host data access command at a primary controller chip coupled to a host device via a primary host interface of the primary controller chip;
• means for transferring the host data access command from the primary controller chip to a secondary controller chip coupled to the primary controller chip via an extension interface of the primary controller chip, wherein a bandwidth of the primary host interface is greater than a bandwidth of the extension interface, the bandwidth of the primary host interface is split between the primary controller chip and the secondary controller chip, and each of the primary controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the primary host interface;
• means for receiving an indication from the secondary controller chip that execution of the transferred host data access command by the secondary controller chip has been completed, wherein a host controller of the secondary controller chip is configured to provide the indication;
• and
• means for notifying the host device, in response to the received indication, that execution of the host data access command has been completed.