US 10,372,198 B2 · Controlling performance states of processing engines of a processor

Abstract

In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Claims17

Dependent claims

A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:

measuring an activity overlap between a first processing engine and a second processing engine of a processor during an evaluation interval, based at least in part on a count value of a counter, wherein the counter is updated when the first processing engine and the second processing engine are concurrently in an active state;
estimating an expected activity overlap between the first processing engine and the second processing engine;
and
responsive to the measured activity overlap exceeding the expected activity overlap, enabling a performance state of at least one of the first processing engine and the second processing engine to be increased.

1 more element

A system comprising:

a processor including a first domain having a plurality of cores, a second domain having at least one graphics engine, and a power controller to control a performance state of the first domain based at least in part on a correlation of execution of a first workload on the first domain and execution of a second workload on the second domain, wherein the correlation comprises a comparison between a random overlap of the execution of the first workload on the first domain and the execution of the second workload on the second domain within a first window and a measured overlap of the execution of the first workload on the first domain and the execution of the second workload on the second domain within the first window, wherein the power controller is further to determine an average number of active cores over the first window, an estimated activity level of the processor for the first window, and adjust a window length at which the power controller is to control the performance state, based at least in part on a comparison of the estimated activity level and the average number of active cores;
and
a dynamic random access memory (DRAM) coupled to the processor.

Dependencies are inferred from the claim text.

Facts

Application

15/686,222Filed 25 Aug 2017 · division

Priority

27 May 2015

Published

US 2017/0371400 A128 Dec 2017

Granted

6 Aug 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency
G06F 1/3243
Power saving characterised by the action undertaken: power saving in microcontroller unit
G06F 1/3296
Power saving characterised by the action undertaken: by lowering the supply or operating voltage

Family

Application14/722,518Parent of this division · filed 27 May 2015

US 2017/0371400 A1Pre-grant publication · published 28 Dec 2017

US 9,760,160 B2Parent of this division

US 2016/0349828 A1Published application

US 10,372,198 B2This patent

From the US filing history. Foreign family members aren’t listed.

Controlling performance states of processing engines of a processor

Life of this patent

Controlling performance states of processing engines of a processor

Life of this patent

Abstract

Claims17