System-on-chip to support full handshake and mobile device having the same

A system-on-chip (SoC) comprising:

• a clock management unit (CMU);
• and
• a logic block configured to transmit a first clock request signal to the CMU,
• wherein the CMU is configured to transmit an acknowledgement signal to the logic block in response to the first clock request signal, the CMU including,
• a manager configured to receive the first clock request signal from the logic block and to output a second clock request signal,
• a gate circuit configured to receive the second clock request signal from the manager and to output a third clock request signal,
• a divider circuit configured to receive the third clock request signal from the gate circuit and to output a fourth clock request signal,
• a multiplexer circuit configured to receive the fourth clock request signal from the divider circuit and output a fifth clock request signal,
• a phase locked loop (PLL) configured to receive the fifth clock request signal and to output a sixth clock request signal, and
• an oscillator pad configured to receive the sixth clock request signal from the PLL, and to output the acknowledgement signal and a first clock signal in response to the sixth clock request signal.

A system-on-chip (SoC) comprising:

• a clock management unit (CMU) including a manager, and a plurality of clock generators configured to generate a plurality of clock signals including a first clock signal and a second clock signal, the plurality of clock generators including a first clock generator configured to generate the first clock signal and a second clock generator configured to generate the second clock signal, the first clock generator including a first full handshake circuit, the second clock generator including a second full handshake circuit;
• and
• a logic block configured to transmit a clock request signal to the CMU,
• wherein the CMU is configured to transmit an acknowledgement signal to the logic block in response to the clock request signal, and
• when the logic block transmits the clock request signal to the CMU during a clock off sequence in which the first clock generator does not generate the first clock signal and the second clock generator does not generate the second clock signal, the manager is configured to transmit a command for blocking the clock off sequence to the first full handshake circuit, the first full handshake circuit is configured to transmit the command for block the clock off sequence to the second full handshake circuit, and the second full handshake circuit is configured to transmit the command for blocking the clock off sequence to other full handshake circuits.