US 10,371,748 B2Granted

Monitoring communication link in powered-up device for synchronization point sequence

AssigneeTexas Instruments Incorporated

InventorGary L. Swoboda

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Abstract

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Claims4

Dependent claims

A process of operating a system comprising:

(a) operating a state machine controller in a first device by receiving clock signals, mode signals, and data in signals on a communication link, and sending data out signals on the communication link;
(b) monitoring the communication link in the first device for a synchronization point sequence;
(c) powering up a state machine controller in a second device coupled to the communication link;
(d) monitoring the communication link in the second device for the synchronization point sequence;
(e) upon receiving the synchronization point sequence in the first device and the second device, synchronizing the states of the state machines in the first and second devices;
and
(f) operating the state machine controller in the first device and the state machine controller in the second device by receiving clock signals, mode signals, and data in signals on the communication link, and sending data out signals on the communication link.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/696,687Filed 6 Sep 2017 · division
Priority: 7 Jun 2007
Published: US 2017/0363686 A121 Dec 2017
Granted: 6 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G01R 31/3177
Testing of digital circuits: testing of logic operation, e.g. by logic analysers
G01R 31/317
Testing of electronic circuits, e.g. by signal tracer: testing of digital circuits
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/3206
Power management, i.e. event-based initiation of a power-saving mode: monitoring of events, devices or parameters that trigger a change in power…

Family

Application60/933,645Us provisional application · filed 7 Jun 2007
Application60/937,388Us provisional application · filed 27 Jun 2007
Application12/134,772Parent of this division · filed 6 Jun 2008
Application13/292,672Parent of this division · filed 9 Nov 2011
US 8,078,898 B2Parent of this division · filed 13 Dec 2011
Application13/489,641Parent of this division · filed 6 Jun 2012
US 8,225,126 B2Parent of this division · filed 17 Jul 2012
Application13/887,989Parent of this division · filed 6 May 2013
US 8,458,505 B2Parent of this division · filed 4 Jun 2013
Application14/635,699Parent of this division · filed 2 Mar 2015
US 9,009,551 B2Parent of this division · filed 14 Apr 2015
US 2017/0363686 A1Pre-grant publication · published 21 Dec 2017
US 9,903,914 B2Parent of this division
US 2008/0304606 A1Published application
US 2012/0060068 A1Published application
US 2012/0254681 A1Published application
US 2013/0246830 A1Published application
US 2015/0168494 A1Published application
US 10,371,748 B2This patent

From the US filing history. Foreign family members aren’t listed.

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