Physically aware scan diagnostic logic and power saving circuit insertion

A computer-implemented method for scan diagnostic logic insertion in a circuit design topology, the method comprising:

• evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain;
• identifying one of the plurality of physical structures as a physical structure of interest;
• responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain, wherein the inserted scan diagnostic logic is at least one of a multiplexor device, NOR circuit, or XNOR circuit;
• disabling a segment of the scan chain associated with the targeted physical structure of interest when the circuit design topology is operating in functional mode to conserve power, wherein the disabling includes providing a scan_disable signal to at least one of the plurality of scan latches;
• outputting a signal to a system, wherein the signal is based at least in part on the evaluation;
• and
• propagating results of the evaluating the scan chain to a central processing unit (CPU).