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US 10,348,316 B2Granted
Frequency division correction circuit, reception circuit, and integrated circuit
AssigneeSocionext Inc.
InventorAtsushi Matsuda
Life of this patent
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Abstract
A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
Claims17
A frequency division correction circuit comprising:
- a first frequency divider configured to perform non-integer frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio;
- and
- a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal, wherein:
- the first frequency divider is configured to output a third frequency division, signal that is a logical inversion signal of the first frequency division signal and a fourth frequency division signal that is a logical inversion signal of the second frequency division signal;
- and
- the corrector is configured to generate a second output signal having an intermediate duty ratio between a duty ratio of the third frequency division signal and a duty ratio of the fourth frequency division signal, based on the third frequency division signal and the fourth frequency division signal.
3 more elements
A reception circuit comprising:
- a frequency division correction circuit configured to generate a first output signal;
- and
- a receiver configured to receive data, based on the first output signal, wherein
- the frequency division correction circuit includes:
- a first frequency divider configured to perform non-integer frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio;
- and
- a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal, wherein:
- the first frequency divider is configured to output a third frequency division signal that is a logical inversion signal of the first frequency division signal and a fourth frequency division signal that is a logical inversion signal of the second frequency division signal;
- and
- the corrector is configured to generate a second output signal having an intermediate duty ratio between a duty ratio of the third frequency division signal and a duty ratio of the fourth frequency division signal, frequency division signal and the fourth frequency division signal.
7 more elements
An integrated circuit comprising:
- a frequency division correction circuit configured to generate a first output signal;
- a receiver configured to receive data, based on the first output signal;
- and
- processing unit configured to process the data received by the receiver, wherein
- the frequency division correction circuit includes:
- a first frequency divider configured to perform non-integer frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio;
- and
- a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal, wherein:
- the first frequency divider is configured to output a third frequency division signal that is a logical inversion signal of the first frequency division signal and a fourth frequency division signal that is a logical inversion signal of the second frequency division signal;
- and
- the corrector is configured to generate a second output signal having an intermediate duty ratio between a duty ratio of the third frequency division signal and a duty ratio of the fourth frequency division signal, based on the third frequency division signal and the fourth frequency division signal.
8 more elements
Dependencies are inferred from the claim text.