Data transfer circuit, imaging circuit device, and electronic apparatus

A data transfer circuit, comprising

• N stages of register sections that are connected in series and that respectively control transfer timings of N analogue signals, where N is an integer that is greater than or equal to 3, wherein
• a register section at an nth (1<n<N) stage includes:
• a first transfer gate that transfers one analogue signal out of the N analogue signals;
• a second transfer gate that transfers one clock out of a clock signal, thereby generating an (n+1)th start signal for a register section at an (n+1)th stage;
• a control signal generation circuit that generates control signals for the first transfer gate and the second transfer gate;
• and
• a holding capacitor whose one end is connected to an output node of the control signal generation circuit, and that holds a voltage of the output node,
• the control signal generation circuit includes a third transfer gate that transfers an nth start signal that is input from a register section at an (n−1)th stage, based on the nth start signal, and
• the third transfer gate is formed as a CMOS logic circuit.