Image capturing method and image capturing apparatus

An image capturing apparatus including a color-separation optical system and CMOS image capturing elements as three or more focal plane shutters, comprising:

• a timing circuit which generates and applies a vertical synchronization signal derived from offsetting vertical synchronization phases of captured image frames of B, G, and R, or B, G1, G2, and R, by approximately half a vertical synchronization period at an even multiple of speed, and generates a vertical synchronization signal without offsetting the vertical synchronization period at an odd multiple of speed;
• a CMOS image capturing element for image capturing of B at a speed of an integer N multiple of a number of output picture frames in synchronization with the vertical synchronization signal derived from offsetting by approximately half the vertical synchronization period at an even multiple of speed;
• a CMOS image capturing element for image capturing of G, or G1 and G2, at a speed of an integer M multiple of an integer N+1 or more in synchronization with the vertical synchronization signal without offsetting the vertical synchronization period at an odd multiple of speed;
• a CMOS image capturing element for image capturing of R at a speed of the integer M multiple of the number of the integer N+1 or more in synchronization with the vertical synchronization signal without offsetting the vertical synchronization period at the odd multiple of speed;
• and
• a picture signal processing circuit including frame speed conversion means,
• wherein the image capturing apparatus comprises at least one of the group consisting of:
• (a) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of R at X2 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of G, or G1 and G2, at X3 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of B at the equal speed, and the CMOS image capturing element of R executes image capturing at X2 speed, the CMOS image capturing element of G, or G1 and G2, executes image capturing at X3 speed, and the CMOS image capturing element of B executes image capturing at the equal speed;
• (b) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X2 speed to the CMOS image capturing element of R at X2 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of G, or G1 and G2, at X2 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of B at the equal speed, and the CMOS image capturing element of R executes image capturing at X2 speed, the CMOS image capturing element of G, or G1 and G2, executes image capturing at X2 speed, and the CMOS image capturing element of B executes image capturing at the equal speed;
• (c) the timing circuit generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of R at X3 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of G, or G1 and G2, at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed, and the CMOS image capturing element of R executes image capturing at X3 speed, the CMOS image capturing element of G, or G1 and G2, executes image capturing at X4 speed, and the CMOS image capturing element of B executes image capturing at X2 speed;
• and
• (d) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of R at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X4 speed to the CMOS image capturing element of G, or G1 and G2, at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed, and the CMOS image capturing element of R executes image capturing at X4 speed, the CMOS image capturing element of G, or G1 and G2, executes image capturing at X4 speed, and the CMOS image capturing element of B executes image capturing at X2 speed.