Differential power analysis resistant encryption and decryption functions

A system, comprising:

• an integrated circuit configured to encrypt data including by:
• partitioning, via circuitry, plaintext into a plurality of blocks, wherein each block of the plurality of blocks is stored in memory;
• generating, via the circuitry, a first sequence of encryption round keys for encrypting a first block of the plurality of blocks from a first cipher key using a key expansion block, wherein one of the first sequence of encryption round keys is generated based at least in part on at least one preceding encryption round key in the first sequence;
• obfuscating, via the circuitry, a substitution table by interleaving the first sequence of encryption round keys with a first set of random data;
• performing, via the circuitry, a cryptographic operation to encrypt the first sequence of encryption round keys using the obfuscated substitution table;
• generating, via the circuitry, a second sequence of encryption round keys for encrypting a second block of the plurality of blocks from a second cipher key, wherein one of the second sequence of encryption round keys is generated based at least in part on at least one preceding encryption round key in the second sequence, and wherein the first cipher key is derived as a function of:
• the second cipher key;
• the second block of the plurality of blocks;
• a block of ciphertext corresponding to the second block of the plurality of blocks;
• an output of a linear feedback shift register (LFSR) associated with the second block of the plurality of blocks;
• or
• any combination thereof;
• obfuscating, via the circuitry, an additional substitution table by interleaving the second sequence of encryption round keys-with a second set of random data;
• performing, via the circuitry, the cryptographic operation to encrypt the second sequence of encryption round keys-using the additional obfuscated substitution table;
• and
• encrypting, via the circuitry, the first block of the plurality of blocks based at least in part on the first encrypted sequence of encryption round keys;
• encrypting, via the circuitry, the second block of the plurality of blocks based at least in part on the second encrypted sequence of encryption round keys;
• and
• transmitting, via the circuitry, the encrypted first block and the encrypted second block to a programmable logic device, wherein the programmable logic device is configured to adjust one or more circuit components of the programmable logic device based at least in part on the encrypted first block and the encrypted second block.