US 10,320,534 B2 · Receiver clock test circuitry and related methods and apparatuses

Abstract

An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.

Claims22

Dependent claims

An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising:

a register to storage at least one programmable parameter;
a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a first mode and when the receiver is operated in a second mode;
circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the first mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the first mode, according to the pattern of variation;
and
circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the first mode.

2 more elements

An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising:

a register to storage at least one programmable parameter;
a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a test mode and when the receiver is operated in a normal mode;
circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the test mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the test mode, according to the pattern of variation;
and
circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the test mode;
wherein the at least one programmable parameter comprises a value established so as cause the circuitry to inject to inject at least one of a random, sinusoidal or spread spectrum jitter pattern into the reference clock.

3 more elements

An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising:

a register to storage at least one programmable parameter;
a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a first mode and when the receiver is operated in a second mode;
circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the first mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the first mode, according to the pattern of variation;
and
circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the first mode;
wherein the first mode is a test mode, wherein integrated circuit further comprises a clock recovery circuit to generate a recovered clock, and wherein the reference clock is based on the recovered clock when the receiver is operated in the first mode.

3 more elements

Dependencies are inferred from the claim text.

Receiver clock test circuitry and related methods and apparatuses

Life of this patent

Receiver clock test circuitry and related methods and apparatuses

Life of this patent

Abstract

Claims22