US 10,320,509 B2 · Fail safe clock buffer and clock generator

Abstract

Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

Claims20

Dependent claims

A fail safe clock generator comprising:

an oscillator circuit configured to generate a clock signal having a short-term stable reference frequency;
and
a monitor circuit comprising:
a frequency-to-digital converter configured to generate a first digital frequency value representing a first frequency of a first input clock signal relative to the short-term stable reference frequency;
a circuit configured to provide a second digital frequency value representing a second frequency relative to the short-term stable reference frequency;
and
a logic circuit configured to generate a fault detection signal based on a difference between the first digital frequency value and the second digital frequency value,
wherein the fail safe clock generator provides an output clock signal based on the difference.

5 more elements

Dependencies are inferred from the claim text.

Fail safe clock buffer and clock generator

Life of this patent

Fail safe clock buffer and clock generator

Life of this patent

Abstract

Claims20