Memory controller, memory system and memory control method

A method for controlling a non-volatile memory, the non-volatile memory including a plurality of memory cells, each of the memory cells having a storage capacity of m bits in accordance with 2 to the power of m threshold voltage distributions, the 2 to the power of m threshold voltage distributions including a first threshold voltage distribution and at least one other threshold voltage distribution, the first threshold voltage distribution indicating an erase state, the at least one other threshold voltage distribution being higher than the first threshold voltage distribution and indicating a write state, where m is a natural number that is equal to or greater than 2, the method comprising:

• performing, via processing circuitry, a first reading to read data from the non-volatile memory, the first reading including a reading performed by using a hard decision voltage, a reading performed by using a first read voltage lower than the hard decision voltage, and a reading performed by using a second read voltage higher than the hard decision voltage, the hard decision voltage being a voltage for a hard decision of the data stored in the non-volatile memory;
• converting first data read by the first reading into first likelihood information;
• decoding data read from the non-volatile memory based on the first likelihood information;
• performing, in a case where the decoding based on the first likelihood information has failed, a second reading, the second reading being reading a plurality of data sets from the non-volatile memory with a plurality of steps, the plurality of steps being performed serially, each of the plurality of steps corresponding to each of a plurality of read voltages at predetermined intervals within a certain voltage range, each of the plurality of data sets corresponding to each of the plurality of read voltages;
• calculating the hard decision voltage using the plurality of data sets;
• updating the hard decision voltage with the calculated hard decision voltage;
• converting the plurality of data sets into second likelihood information;
• and
• decoding data read from the non-volatile memory based on the second likelihood information, wherein
• the 2 to the power of m threshold voltage distributions are the first threshold voltage distribution and a second to a k-th threshold voltage distribution, where k is 2 to the power of m,
• a voltage corresponding to the (n+1)-th threshold voltage distribution is higher than a voltage corresponding to the n-th threshold voltage distribution, where n is natural number equal to or greater than 1 and smaller than k,
• the certain voltage range is a range over the second to the k-th threshold voltage distributions,
• in the first reading using the hard decision voltage between a center of the n-th threshold voltage distribution and a center of the (n+1)-th threshold voltage distribution, the first read voltage and the second read voltage are higher than the center voltage of the n-th threshold voltage distribution and lower than the center voltage of the (n+1)-th threshold voltage distribution,
• a voltage range between the first read voltage and the second read voltage is narrower than a range from the n-th threshold voltage distribution to the (n+1)-th threshold voltage distribution,
• each of the plurality of data sets includes a plurality of bits, each of the plurality of bits indicating whether current flows each of the plurality of memory cells,
• the processing circuitry calculates the number of memory cells in the plurality of memory cells, and a threshold voltage of which being corresponding to one of the plurality of read voltages, based on the plurality of bits, with respect to each of the plurality of read voltages, and
• the processing circuitry calculates the hard decision voltage based on the calculated number of memory cells.