Staircase forward error correction coding

An apparatus that comprises:

• an interface to receive a sequence of FEC encoded two-dimensional symbol blocks Bi, i a positive integer, each of the received symbol blocks comprising received versions of data symbols at data symbol positions and coding symbols at coding symbol positions, the coding symbols for the coding symbol positions in each symbol block Bi in the sequence having been processed at a transmitter of the received symbol blocks such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with symbols at symbol positions along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code;
• and
• an FEC decoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the interface, to decode the received FEC encoded symbol blocks,
• wherein each symbol block comprises an n row by m column array of symbols, m, n>1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block Bi based on Di−1 and Bi, where Di−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of Bi−1.