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US 10,320,401 B2Granted
Dual-path digital-to-time converter
AssigneeXilinx, Inc.
InventorsAugusto R. Ximenes, Bob W. Verbruggen, Christophe Erdmann
Life of this patent
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Abstract
An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
Claims18
A digital-to-time converter (DTC), comprising:
- a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer;
- and
- a dynamic element matching (DEM) controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
A digital phase-locked loop (DPLL), comprising:
- a digitally controlled oscillator (DCO) configured to generate a clock signal;
- and
- a digital-to-time converter (DTC) having first input coupled to an output of the DCO and a second input configured to receive a reference clock signal, the DTC including:
- a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive the reference clock signal and a second input to receive the clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer;
- and
- a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
3 more elements
A method of digital-to-time conversion, comprising:
- coupling a first clock signal to a first delay path and a second clock signal to a second delay path, each of the first and second delay paths implemented by a delay chain circuit having a plurality of delay cells coupled in sequence, wherein each of the plurality of delay cells includes a multiplexer and first and second delay circuits coupled to the multiplexer;
- providing a plurality of control signals to the plurality of delay cells to adjust delay of the first delay path with respect to the second delay path.
Dependencies are inferred from the claim text.